发明名称 |
Systems, methods, and programs for leakage power and timing optimization in integrated circuit designs |
摘要 |
A method, system and program for reducing or optimizing leakage power consumption in an integrated circuit produced in accordance with an integrated circuit model. A fast corner timing database and configurable timing constraints are used in conjunction with hold cell logic to identify a set of cells that should not be modified. A leakage optimization procedure is responsive to a slow corner timing database and timing constraints for a slow corner. The procedure is configurable and includes the repair of register transition violations. The procedure is performed on a select number of paths before an adjusted timing slack value is determined and cells are addressed in response to the number of failing timing paths associated with a cell. Some embodiments generate information in a router compatible format that identifies a desired modification to the top-level integrated circuit design. |
申请公布号 |
US8332802(B2) |
申请公布日期 |
2012.12.11 |
申请号 |
US20100911156 |
申请日期 |
2010.10.25 |
申请人 |
HAUGESTUEN BENJAMIN P.;PORTER HOWARD L.;RODGERS RICHARD;AVAGO TECHNOLOGIES ENTERPRISE IP (SINGAPORE) PTE.LTD. |
发明人 |
HAUGESTUEN BENJAMIN P.;PORTER HOWARD L.;RODGERS RICHARD |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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