发明名称 Instruction check program, instruction check apparatus, and I/O simulator
摘要 A computer-readable medium encoded with an instruction check program for making a computer to check a status of execution of an instruction by an I/O simulator that performs an operation simulation according to a structure of an I/O area of a microcomputer, the instruction check program when executed by a computer causes the computer to perform a method including obtaining specification information of the microcomputer describing an input and an output condition of a hardware resource in the I/O area, detecting a simulation of a reference instruction to the hardware resource executed by the I/O simulator, determining correctness of the reference instruction by comparing a content of the simulation of the reference instruction detected by the detecting with the input and output condition of the hardware resource included in the obtained specification information, and outputting an error signal when it is determined that the reference instruction is incorrect.
申请公布号 US8332204(B2) 申请公布日期 2012.12.11
申请号 US20080343767 申请日期 2008.12.24
申请人 WATANABE MANABU;FUJITSU SEMICONDUCTOR LIMITED 发明人 WATANABE MANABU
分类号 G06F9/455 主分类号 G06F9/455
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