发明名称 |
Digital second-order CDR circuits |
摘要 |
A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (FSM) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from the second-order phase code. A multiplexing is performed to the plurality of candidate total phase codes to output one of the plurality of candidate total phase codes as a total phase code. The multiplexing is controlled by the first-order phase code. A brake machine may be implemented to prevent over-compensation of phases. |
申请公布号 |
US8331514(B2) |
申请公布日期 |
2012.12.11 |
申请号 |
US20100762158 |
申请日期 |
2010.04.16 |
申请人 |
FU CHIN-MING;YU TSUNG-HSIN;LU CHI-CHANG;CHEN WEI CHIH;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
FU CHIN-MING;YU TSUNG-HSIN;LU CHI-CHANG;CHEN WEI CHIH |
分类号 |
H04L7/00 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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