| 摘要 |
A flash memory according to a present embodiment includes a memory cell array. The memory cell array includes a plurality of memory cells. Each of the memory cells can store n-bit data (n is an integer equal to or larger than 2). A plurality of word line are connected to gate terminals of the memory cells. A plurality of bit lines are connected to the memory cells. Sense amplifiers are configured to detect data stored in the memory cells via the bit lines. A data latch circuit of m×n bits can store n-bit data stored in each of m memory cells (m is an integer equal to or larger than 2) connected to one of the word lines. A multi-level interface can simultaneously transfer data of two or more bits between the data latch circuit and outside. |
