发明名称 MEMORY SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To reduce risk of producing large noise at time of reading data in a memory system in which a plurality of memory devices are commonly connected to a memory controller. <P>SOLUTION: The memory system comprises: a memory controller 32; and a plurality of memory devices 12a-12d. Each data terminal 20d of the memory devices 12a-12d is commonly connected to the memory controller 32. The memory device 12 includes a memory cell array 14 and a data output circuit 18 that outputs data read from the memory cell array 14. Timing when the memory devices 12a-12d output data is adjusted to be different from each other. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012243251(A) 申请公布日期 2012.12.10
申请号 JP20110115865 申请日期 2011.05.24
申请人 ELPIDA MEMORY INC 发明人 ISHIKAWA TORU
分类号 G06F12/00 主分类号 G06F12/00
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