发明名称 OUTPUT INTERFACE CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide an output interface circuit capable of suppressing the fluctuation of a power source voltage while preventing the consumption of a large amount of currents. <P>SOLUTION: A first transistor Tr1 is arranged between a power source and ground, where a control voltage is connected to a first node. A first capacitor 43 is arranged between the first node B and the ground. A control buffer 41 receives the respective bits of data input from an external part at timing being the same as that of an output buffer 110, whose output is connected to the first node B. A second transistor Tr2 is arranged between the power source and the ground, where a control electrode is connected to a second node C. A second capacitor 44 is arranged between the second node C and the ground. A control inverter 42 receives the respective bits of data input from an external part at timing being the same as that of the output buffer 110, whose output is connected to the second node C. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012244332(A) 申请公布日期 2012.12.10
申请号 JP20110111308 申请日期 2011.05.18
申请人 RENESAS ELECTRONICS CORP 发明人 SUGA YASUHIRO;AOYANAGI KEISUKE
分类号 H04L25/02;H03K19/0175;H03K19/096 主分类号 H04L25/02
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