发明名称 PROCESSING METHOD OF SILICON WAFER AND THREE-DIMENSIONAL SILICON INTERPOSER AND CHIP SIZE PACKAGE
摘要 <P>PROBLEM TO BE SOLVED: To provide a technology of forming an identification symbol directly on a silicon wafer, in a chip size package or a three-dimensional stacked package where it is indispensable to form a through hole in a silicon wafer. <P>SOLUTION: The processing method of a silicon wafer comprises: a coating step for coating a silicon wafer with a photosensitive resist; an exposure step for exposing the photosensitive resist through a concentration distribution mask having a predetermined pattern; a development step for forming an aperture through which the silicon wafer is exposed and an aperture through which the silicon wafer is not exposed in the photosensitive resist; a step for simultaneously forming identification symbols consisting of a through hole and a non-through hole for conduction in the silicon wafer by removing the silicon wafer at a part corresponding to the aperture of the photosensitive resist by dry etching; and a step for removing the residual photosensitive resist. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012243897(A) 申请公布日期 2012.12.10
申请号 JP20110111233 申请日期 2011.05.18
申请人 TOPPAN PRINTING CO LTD 发明人 AKIYAMA NAOYUKI
分类号 H01L21/027;G03F7/20;H01L21/3065;H01L23/32 主分类号 H01L21/027
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