| 摘要 |
<P>PROBLEM TO BE SOLVED: To make it possible to speed up serial data communication designed and configured by the PLC, and in addition, to make it possible to clear a jitter allowable range of reception data. <P>SOLUTION: In a DPLL circuit 10, data shift circuits DS1-DS3 generate a plurality of pieces of serial data synchronized with a source clock CLK from reception data. An exclusive OR circuit EX_OR detects a change point of the reception data from a pair of pieces of serial data. A counter DPLCNT, whose maximum count value, n, is set, counts a source clock from the change point to the next change point. An accordance determination circuit AND outputs a clock as a reception clock when the count value of the counter accords with a preset count value, n halves. A high-level data link controller module (HDLC-IP) 20 performs transfer control of the reception data (serial data) with the use of the reception clock. <P>COPYRIGHT: (C)2013,JPO&INPIT |
