发明名称 SILICON WAFER ALIGNMENT METHOD USED IN THROUGH-SILICON-VIA INTERCONNECTION
摘要 A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance.
申请公布号 US2012309118(A1) 申请公布日期 2012.12.06
申请号 US201113304149 申请日期 2011.11.23
申请人 WANG PENGFEI;SUN QINGQING;DING SHIJIN;ZHANG WEI;FUDAN UNIVERSITY 发明人 WANG PENGFEI;SUN QINGQING;DING SHIJIN;ZHANG WEI
分类号 H01L21/66 主分类号 H01L21/66
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