| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress an inflow of a large current into a memory macro when a semiconductor storage device returns from a power-down mode to a normal operation mode. <P>SOLUTION: An SRAM macro 100 includes the normal operation mode for allowing an access to a plurality of memory cell array blocks and the power-down mode for floating bit lines BL and /BL of the plurality of memory cell array blocks. When returning from the power-down mode to the normal operation mode, the semiconductor storage device sequentially precharges only the bit lines BL and /BL of a memory cell array block 11 to be accessed out of the plurality of memory cell array blocks. This constitution can distribute a peak of the current flowing in the SRAM macro 100 that is required for the precharge. <P>COPYRIGHT: (C)2013,JPO&INPIT |
