发明名称
摘要 <p>The invention concerns an apparatus (10) for data processing comprising a central processing unit (12) and a non volatile random access memory (34). The central processing unit (12) and the non volatile random access memory (34) are connected via a memory bus (14, 16, 20, 32). The data related to an operating system for running said apparatus (10) is at least partly stored in said non volatile random access memory (34) and the memory used by the operating system for operating said apparatus (10) is at least partly said non volatile memory (34).</p>
申请公布号 JP2012530991(A) 申请公布日期 2012.12.06
申请号 JP20120516639 申请日期 2010.06.15
申请人 发明人
分类号 G06F12/06;G06F12/00 主分类号 G06F12/06
代理机构 代理人
主权项
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