发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT WITH MULTI-CUT VIA AND AUTOMATED LAYOUT METHOD FOR THE SAME
摘要 A semiconductor integrated circuit includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first overlap area, a second overlap area, a multi-cut via, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring in the second overlap area. A width of the second portion of the second wiring corresponding to a first direction is longer than a width of the first portion of the second wiring corresponding to the first direction. A distance between the center of the first via and the center of the second via is longer than the width of the first portion of second wiring.
申请公布号 US2012306083(A1) 申请公布日期 2012.12.06
申请号 US201213586070 申请日期 2012.08.15
申请人 NISHIMUDA KEIICHI;RENESAS ELECTRONICS CORPORATION 发明人 NISHIMUDA KEIICHI
分类号 H01L23/535 主分类号 H01L23/535
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