发明名称 SYSTEM AND METHOD FOR GATE TRAINING IN A MEMORY SYSTEM
摘要 A system and method for gate training in a memory system is disclosed. In one embodiment, in a method for calibrating read data strobe gating, a first read command is issued to a memory module. A first DQS gate signal is issued before the beginning of the preamble of a first DQS signal received from the memory module that corresponds to the first read command. A second read command is issued to the memory module such that the preamble of a second DQS signal received from the memory module that corresponds to the second read command is adjacent to the postamble of the first DQS signal. Then, a second DQS gate signal is issued at a preset time after the first DQS gate signal. The second DQS signal is sampled repeatedly to locate the preamble of the second DQS signal.
申请公布号 US2012307577(A1) 申请公布日期 2012.12.06
申请号 US201113118499 申请日期 2011.05.30
申请人 SRIADIBHATLA SRINIVAS;WEBSTER CURTIS MATHESON 发明人 SRIADIBHATLA SRINIVAS;WEBSTER CURTIS MATHESON
分类号 G11C7/22 主分类号 G11C7/22
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