Current reduction in a single stage cyclic analog to digital converter with variable resolution

摘要

A converter (200) adapted to convert an analog input signal (VIN) into a digital output signal includes an analog input terminal (205) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage (210, 300) coupled to the analog input terminal, and a digital section (220). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits (D0, D1, D2) at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal (VR) of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits (D0, D1) at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.