| 摘要 |
PURPOSE: A micro controller and an operation method are provided to reduce a miss ratio which a main processor senses by using two or more internal buffer memories. CONSTITUTION: First and second caches(320,330) store an instruction or a program code. A cache controller(340) stores the instruction or the program code, which is read from an external memory, in any one of the first cache or the second cache. A cache bridge controller(310) searches the instruction or the program code, which is requested in a processor(210), in the first cache or the second cache. The cache bridge controller delivers the instruction or the program code to the processor. The cache controller determines a cache which is able to currently store based on operation state information of the first cache or the second cache. [Reference numerals] (210) Processor; (220) External memory; (310) Cache bridge controller; (320) First cache; (330) Second cache; (340) Cache controller; (350) Error correction module; (360) S-Flash controller; (370) Clock converter
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