| 摘要 |
An integrated circuit designing apparatus for designing a semiconductor integrated circuit. The designing includes verifying the timing based on delay information included in the design data, the delay information is extracted from results of placing and wiring of the semiconductor integrated circuit; determining whether each value of hold-time errors generated as a result of the timing verification is smaller than a criteria value; extracting, when the value of a hold-time error is smaller than the criteria value, a wiring line in which the hold-time error is improved by performing a wiring line extension process, the wiring line is included in a path having the hold-time error; calculating, for the extracted wiring line, a wiring line extension distance corresponding to an insertion delay value that improves the hold-time error; and performing the wiring line extension process to extend the extracted wiring line by the calculated wiring line extension distance. |
