| 摘要 |
Described herein are system(s) and method(s) for routing data in a parallel Turbo decoder. Aspects of the present invention address the need for reducing the physical circuit area, power consumption, and/or latency of parallel Turbo decoders. According to certain aspects of the present invention, address routing-networks may be eliminated, thereby reducing circuit area and power consumption. According to other aspects of the present invention, address generation may be moved from the processors to dedicated address generation modules, thereby decreasing connectivity overhead and latency. |
