Reconfigurable FADEC with flash based FPGA control channel and ASIC sensor signal processor for aircraft engine control

摘要

A reconfigurable FADEC includes a reconfigurable CPU configured for performing digital computing functions. A reconfigurable MSPD communicates with the CPU and is configured for performing analog I/O functions. A data bus is coupled to the CPU and the MSPD. The data bus is configured for connecting the CPU and the MSPD to an external connector.