发明名称 Process for manufacturing a MOS device with intercell ion implant confined to the gate electrode region
摘要 A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region, above the semiconductor layer; forming body regions having a second type of conductivity, within the semiconductor layer, laterally and partially underneath the insulated gate structure; forming source regions having the first type of conductivity, within the body regions; and forming a first enrichment region, in a surface portion of the semiconductor layer underneath the insulated gate structure. The first enrichment region has the first type of conductivity and is set at a distance from the body regions. In order to form the first enrichment region, a first enrichment window is defined within the insulated gate structure, and first dopant species of the first type of conductivity are introduced through the first enrichment window and in a way self-aligned thereto.
申请公布号 US8324669(B2) 申请公布日期 2012.12.04
申请号 US201113292003 申请日期 2011.11.08
申请人 CURRO GIUSEPPE;STMICROELECTRONICS S.R.L. 发明人 CURRO GIUSEPPE
分类号 H01L29/76 主分类号 H01L29/76
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