发明名称 |
METHODS AND APPARATUS TO IMPROVE RELIABILITY OF ISOLATED VIAS |
摘要 |
A method for tiling selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and adding tiling features on a metal layer above the selected isolated vias and within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.
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申请公布号 |
US2012299190(A1) |
申请公布日期 |
2012.11.29 |
申请号 |
US201113114100 |
申请日期 |
2011.05.24 |
申请人 |
REBER DOUGLAS M.;HERR LAWRENCE N. |
发明人 |
REBER DOUGLAS M.;HERR LAWRENCE N. |
分类号 |
H01L23/48;G06F17/50 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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