发明名称 |
FET with FUSI Gate and Reduced Source/Drain Contact Resistance |
摘要 |
A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.
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申请公布号 |
US2012299102(A1) |
申请公布日期 |
2012.11.29 |
申请号 |
US201213569741 |
申请日期 |
2012.08.08 |
申请人 |
LAVOIE CHRISTIAN;NING TAK H.;OUYANG QIQING;SOLOMON PAUL;ZHEN ZHANG;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LAVOIE CHRISTIAN;NING TAK H.;OUYANG QIQING;SOLOMON PAUL;ZHEN ZHANG |
分类号 |
H01L29/786 |
主分类号 |
H01L29/786 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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