发明名称 Accelerating Data Packet Parsing
摘要 Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.
申请公布号 US2012300642(A1) 申请公布日期 2012.11.29
申请号 US201213570343 申请日期 2012.08.09
申请人 ABEL FRANCOIS;CALVIGNAC JEAN L.;CHANG CHIH-JEN;DAMON PHILIPPE;VERPLANKEN FABRICE J.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ABEL FRANCOIS;CALVIGNAC JEAN L.;CHANG CHIH-JEN;DAMON PHILIPPE;VERPLANKEN FABRICE J.
分类号 H04L12/56;H04L12/26 主分类号 H04L12/56
代理机构 代理人
主权项
地址