发明名称 DATA PROCESSING SYSTEM WITH LATENCY TOLERANCE EXECUTION
摘要 In a processor having an instruction unit, a decode/issue unit, and execution queues configured to provide instructions to correspondingly different types execution units, a method comprises maintaining a duplicate free list for the execution queues. The duplicate free list includes a plurality of duplicate dependent instruction indicators that indicate when a duplicate instruction for a dependent instruction is stored in at least one of the execution queues. One of the duplicate dependent instruction indicators is assigned to an execution queue for a dependent instruction. The dependent instruction is executed only when the one of the duplicate dependent instruction indicators is reset.
申请公布号 US2012303936(A1) 申请公布日期 2012.11.29
申请号 US201213419531 申请日期 2012.03.14
申请人 TRAN THANG M.;NGUYEN TRINH HUY;FREESCALE SEMICONDUCTOR, INC. 发明人 TRAN THANG M.;NGUYEN TRINH HUY
分类号 G06F9/30;G06F9/312;G06F9/34 主分类号 G06F9/30
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