| 摘要 |
The purpose of this invention is to provide a scanning signal line driving circuit with increased reliability of switching elements while reducing power consumption. In the vertical blanking interval, an end signal (ED) changes from the low level to the high level. The potential of the 1st through (m-1)st stage first nodes (N1) of cascade-connected m-stage bistable circuits contained in a shift register of the scanning signal line driving circuit is reliably maintained at the low level, and the potential of 1st through (m-1)st stage second nodes (N2) changes from the high level to the low level. In the mth stage bistable circuit, the potential of the mth stage first node (N1) changes from the high level to the low level, and the potential of the mth stage second node (N2) is maintained at the low level. Further, supply of the clock signal (CKA, CKB) to the bistable circuit is stopped. Until the write period in the subsequent vertical scanning period, the potential of the first nodes (N1) and the potential of the second nodes (N2) in each stage is maintained at the low level. |
