发明名称 DMA DATA TRANSFER MECHANISM TO REDUCE SYSTEM LATENCIES AND IMPROVE PERFORMANCE
摘要 A method of implementing a data transfer mechanism to reduce latencies and improve performance comprising the steps of reading a first data element, storing the first data element, and writing the first data element. The first data element may be read from a host. The first data element may be stored in a storage portion of a controller. The first data element may be written to a first destination device. The first data element may also be written to a second destination device prior to deleting the first data element from the storage portion.
申请公布号 US2012303840(A1) 申请公布日期 2012.11.29
申请号 US201113114303 申请日期 2011.05.24
申请人 SINGH GURVINDER P. 发明人 SINGH GURVINDER P.
分类号 G06F13/28 主分类号 G06F13/28
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