发明名称 MULTILAYER SEMICONDUCTOR PACKAGE
摘要 <P>PROBLEM TO BE SOLVED: To provide a multilayer semiconductor package which reduces a dimension of a multi-chip module in which a die or chip is laminated. <P>SOLUTION: A semiconductor package 100 includes a semiconductor die 120 mounted on an upper side thereof, and a base substrate 130 above which an interposer substrate 110 is disposed being mounted on an upper portion of the die. A bottom side of the interposer substrate is electrically connected to an upper side of the base substrate by vertical connectors 150. An upper side of the interposer substrate which is substantially exposed includes input-output terminals 140 so that additional electronic components are mounted thereon. The base substrate 130 and interposer substrate 110 include the input-output terminals so that the components mounted on these substrates are electrically connected by the vertical connectors 150. This base substrate can also be electrically connected to a printed circuit board. The vertical connectors 150 are disposed along a number of side portions of the package, so that a routing space between the substrates is increased. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012235170(A) 申请公布日期 2012.11.29
申请号 JP20120193098 申请日期 2012.09.03
申请人 STATS CHIPPAC INC 发明人 PENDSE RAJENDRA D
分类号 H01L25/10;H01L25/11;H01L25/18 主分类号 H01L25/10
代理机构 代理人
主权项
地址