| 摘要 |
<p>An voltage tolerant protection circuit for input buffer comprising a transmission gate circuit (11) receiving input from a pad for passing the input signal to the input of the input buffer, a control signal generator (12) connected between said transmission gate circuit (11) and the pad to provide a control signal (PMOSCTRL) for operating said transmission gate circuit (11), and an N-Well generation circuit (13) connected between the pad and said transmission gate circuit (11), and also connected to said control signal generator (12) for generating a bias signal (NWELL) for said transmission gate circuit (11) and said control signal generator (12). Thus, the present invention provides a voltage tolerant protection circuit that prevents electrical stress on transistors comprised within the transmission gate circuit (11) and the control signal generator (12), minimizes power supply consumption and transfers signals without any change in amplitude. <IMAGE></p> |
