发明名称 processing pipeline control
摘要 A graphics processing unit (2, Fig. 1) includes a texture pipeline 6 having a first pipeline portion 18 and a second pipeline portion 20. A subject instruction, which is part of a program thread and uses target data, is recirculated within the first pipeline portion 18 until descriptor data to be loaded from a memory (4, Fig. 1) by that subject instruction has been fetched and cached within a shared descriptor cache (22, Fig. 1). First gating stage 28 determines when the descriptor has been stored within the cache, and then passes the subject instruction to the second pipeline portion 20. Second gating stage 30 recirculates the subject instruction in the second portion until further processing operations have completed. The descriptor data is locked within the cache until there are no pending subject instructions within pipeline 6 related to that descriptor data. Intervening stages 24 are included between first and second pipeline portions. State data of subject instructions specifying storage locations of the target data within descriptor cache are stored as the instructions pass through the pipeline. State data identifies instructions within a group that shares target data, for example relating to four adjacent pixels processed as a quad.
申请公布号 GB2491156(A) 申请公布日期 2012.11.28
申请号 GB20110008769 申请日期 2011.05.25
申请人 ARM LIMITED 发明人 JA¸RN NYSTAD;ANDREAS DUE ENGH-HALSTVEDT
分类号 G06F9/38;G06F12/08;G06T1/20 主分类号 G06F9/38
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