发明名称 |
Software reconfigurable digital phase lock loop architecture |
摘要 |
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle. |
申请公布号 |
US8321489(B2) |
申请公布日期 |
2012.11.27 |
申请号 |
US20070853575 |
申请日期 |
2007.09.11 |
申请人 |
STASZEWSKI ROMAN;STASZEWSKI ROBERT B.;SHI FUQIANG;NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
STASZEWSKI ROMAN;STASZEWSKI ROBERT B.;SHI FUQIANG |
分类号 |
G06F17/10 |
主分类号 |
G06F17/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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