发明名称 |
Semiconductor integrated circuit device |
摘要 |
A memory device including memory cells each have two transistors and one storage element connected in series in this order between a corresponding one of bit lines and a constant voltage. The two transistors respectively have gate electrodes respectively connected to a corresponding one of first word lines and a corresponding one of second word lines. A memory array includes mats each having the memory cells disposed at all intersections between the bit lines and the first word lines, sense amplifiers each input with a corresponding pair of the bit lines in the same mat as a bit line pair, and first and second word drivers adapted to activate the first and second word lines, respectively. |
申请公布号 |
US8320155(B2) |
申请公布日期 |
2012.11.27 |
申请号 |
US20100801539 |
申请日期 |
2010.06.14 |
申请人 |
SUZUKI RYOTA;ISHIZUKA KAZUTERU;ELPIDA MEMORY, INC. |
发明人 |
SUZUKI RYOTA;ISHIZUKA KAZUTERU |
分类号 |
G11C11/22 |
主分类号 |
G11C11/22 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|