Flip-flop circuit and leakage current suppression circuit utilized in a flip-flop circuit

摘要

A flip-flop circuit includes a D flip-flop and a leakage current suppression circuit. The D flip-flop receives an input signal and a clock signal, and outputs a voltage of the input signal at a rising or falling edge of the clock signal as an output signal. The leakage current suppression circuit detects an output error caused by the leakage current flowing through at least a floating node of the D flip-flop and compensates for the leakage current to correct the output error. The leakage current suppression circuit includes a detection circuit and a compensation circuit. The detection circuit receives the output signal and clock signal and detects whether the output error has occurred to generate a detection result. The compensation circuit compensates for the leakage current according to the detection result to correct the output error.