发明名称 |
Fast data access mode in a memory device |
摘要 |
A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode. |
申请公布号 |
US8321713(B2) |
申请公布日期 |
2012.11.27 |
申请号 |
US20090611458 |
申请日期 |
2009.11.03 |
申请人 |
NOBUNAGA DEAN;MICRON TECHNOLOGY, INC. |
发明人 |
NOBUNAGA DEAN |
分类号 |
G06F1/04;G06F1/12;G11C7/10;G11C7/22 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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