发明名称 Depletion MOS transistor and enhancement MOS transistor
摘要 A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.
申请公布号 US8319316(B2) 申请公布日期 2012.11.27
申请号 US20100788784 申请日期 2010.05.27
申请人 KUTSUKAKE HIROYUKI;GOMIKAWA KENJI;KATO YOSHIKO;NOGUCHI MITSUHIRO;ENDO MASATO;KABUSHIKI KAISHA TOSHIBA 发明人 KUTSUKAKE HIROYUKI;GOMIKAWA KENJI;KATO YOSHIKO;NOGUCHI MITSUHIRO;ENDO MASATO
分类号 H01L21/02 主分类号 H01L21/02
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