| 摘要 |
PURPOSE: A semiconductor device forming a high resistant voltage metal insulator semiconductor field effect transistor and a resistance element on the same board and a manufacturing method thereof are provided to simultaneously planarizing the surface of a semiconductor substrate and reduce a chip size by reducing a rate of a dummy active region to a total area of the semiconductor substrate. CONSTITUTION: A element isolation groove(2) is formed on the front side of a semiconductor substrate(1). An n-type buried layer(3) and a p-type buried layer(4) are formed on a deep domain of the semiconductor substrate. An n-type well(5) functions as a source and a drain of a high resistant voltage n-channel type MISFET(metal insulator semiconductor field effect transistor). A P-type well(6) serves as a part of a source and a drain of a high resistant voltage p-channel type MISFET. A gate insulating layer(7) is formed on the surface of the semiconductor substrate. A resistance element(IR) is formed on the upper part of the gate insulating layer. [Reference numerals] (AA) 7: gate insulating layer; (BB) IR: resistance element |
