发明名称 FETCH LESS INSTRUCTION PROCESSING (FLIP) COMPUTER ARCHITECTURE FOR CENTRAL PROCESSING UNITS (CPU)
摘要 Fetch Less Instruction Processing (FLIP) Computer Architecture for Central Processing Units (CPU). This invention relates to computing systems, and more particularly to central processing units in computing systems. The principal object of this invention is to provide a fetch less instruction processing (FLIP) computer architecture using FLIP elements as building blocks for computer program processing. Another object of the invention is to use a protocol to interconnect FLIP elements, which makes the current operating systems, program execution models, compilers, libraries and so on to be easily transitioned to the FLIP computer architecture with minimal changes.
申请公布号 WO2012156995(A2) 申请公布日期 2012.11.22
申请号 WO2012IN00349 申请日期 2012.05.14
申请人 MELANGE SYSTEMS (P) LIMITED;ATTILI, NARAIN 发明人 ATTILI, NARAIN
分类号 G06F1/16 主分类号 G06F1/16
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