| 摘要 |
A chip size estimating apparatus for a semiconductor integrated circuit of an embodiment has an input section configured to input a minimum number of functional gates that is a minimum number of gates necessary for realization of a function of a circuit, a set value holding section in which a performance-considered number-of-gates coefficient that is a ratio of a number of gates to be necessary for achievement of a predetermined operation speed to the minimum number of functional gates is set in advance for each cell library, and a calculating section configured to estimate a total area of the circuit by using a number of gates that is calculated from the minimum number of functional gates and the performance-considered number-of-gates coefficient.
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