发明名称 Vector processor with plural arithmetic units for processing a vector data string divided into plural register banks accessed by read pointers starting at different positions
摘要 It is an object to speed up a vector store instruction on a memory that is divided into banks as setting a plurality of elements as a unit while minimizing an increase in physical quantity. A vector processing apparatus has a plurality of register banks and processes a data string including a plurality of data elements retained in the plurality of register banks, wherein: the plurality of register banks each have a read pointer 113 that points to a read position for reading the data elements; and the start position of the read pointer 113 is changed from one register bank to another. For example, consecutive numbers assigned to the register banks may be used as the read start positions of the respective register banks.
申请公布号 US8316215(B2) 申请公布日期 2012.11.20
申请号 US20080529892 申请日期 2008.03.07
申请人 HOSHI NORITAKA;NEC CORPORATION 发明人 HOSHI NORITAKA
分类号 G06F15/80 主分类号 G06F15/80
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