发明名称 Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout
摘要 A method of interconnecting a first plurality of electronic components and a second plurality of electronic components to form an electronic circuit includes exporting a first netlist representing a first interconnection of the first electronic components in a first design entry tool, exporting a second netlist representing a second interconnection of the second electronic components in a second design entry tool, providing at least a first interface from the second plurality to the first plurality in the second design entry tool, populating the first interface through the first design entry tool, and exporting a third netlist representing the first interface from the second plurality to the first plurality from the second design entry tool, wherein the third netlist stitches the first netlist to the second netlist.
申请公布号 US8316342(B1) 申请公布日期 2012.11.20
申请号 US20100792325 申请日期 2010.06.02
申请人 KUKAL TARANJIT;CHEUNG CHRIS;KOHLI VIKAS;FELTON KEITH;FARMAR FRANK X.;DURRILL STEVEN R.;CADENCE DESIGN SYSTEMS, INC. 发明人 KUKAL TARANJIT;CHEUNG CHRIS;KOHLI VIKAS;FELTON KEITH;FARMAR FRANK X.;DURRILL STEVEN R.
分类号 G06F17/50;G06F15/04 主分类号 G06F17/50
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