发明名称 Segment and bipartite graph based apparatus and method to address hold violations in static timing
摘要 A method of reducing the number of hold violations in an integrated circuit comprises: determining a segment, wherein the segment is a connection between a plurality of points; associating at least one path with each segment, wherein the path is a connection of points including a starting point and an endpoint; determining a weight for at least one said segment, wherein the weight is determined by a number of paths associated with the at least one said segment; ranking the segments in a matrix based upon the determined weight associated with at least one of the segments; and inserting a buffer at least one of the segments based upon said ranking.
申请公布号 US8316334(B2) 申请公布日期 2012.11.20
申请号 US20100699964 申请日期 2010.02.04
申请人 NAGARAJ KELAGERI;RAJ SATISH K.;SANAKA VENUGOPAL;DASEGOWDA RAGHAVENDRA C.;QUALCOMM INCORPORATED 发明人 NAGARAJ KELAGERI;RAJ SATISH K.;SANAKA VENUGOPAL;DASEGOWDA RAGHAVENDRA C.
分类号 G06F17/50 主分类号 G06F17/50
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