发明名称 Error-correction decoder employing multiple check-node algorithms
摘要 In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). The CNUs generate check-node messages using a scaled min-sum algorithm, an offset min-sum algorithm, or a scaled and offset min-sum algorithm. Initially, the controller selects a scaling factor and an offset value. The scaling factor may be set to one for no scaling, and the offset value may be set to zero for no offsetting. If the decoder is unable to correctly decode a codeword, then (i) the controller selects a new scaling and/or offset value and (ii) the decoder attempts to correctly decode the codeword using the new scaling and/or offset value. By changing the scaling factor and/or offset value, LDPC decoders of the present invention may be capable of improving error-floor characteristics over LDPC decoders that use only fixed or no scaling factors or fixed or no offsetting factors.
申请公布号 US8316272(B2) 申请公布日期 2012.11.20
申请号 US20090680810 申请日期 2009.04.08
申请人 GUNNAM KIRAN;LSI CORPORATION 发明人 GUNNAM KIRAN
分类号 H03M13/00 主分类号 H03M13/00
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