发明名称 CIRCUIT INTERNE DE TENSION D'ALIMENTATION D'UN CIRCUIT INTEGRE
摘要 <p>The disclosure relates to a method for generating a setpoint voltage in an integrated circuit, comprising generating a substantially constant reference voltage, and generating from the reference voltage, a setpoint voltage comprising a component equal to the highest threshold voltage of all the CMOS transistors of a circuit of the integrated circuit and a component which may be equal to zero. The disclosure applies in particular to the provision of a power supply voltage of a circuit based on CMOS transistors.</p>
申请公布号 FR2957161(B1) 申请公布日期 2012.11.16
申请号 FR20100000848 申请日期 2010.03.02
申请人 STMICROELECTRONICS ROUSSET SAS 发明人 LA ROSA FRANCESCO
分类号 G05F3/24;H03H11/54 主分类号 G05F3/24
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