| 摘要 |
In a circuit in FIG. 1, pluses are input to a first gate signal line and a second gate signal line in accordance with a timing chart in FIG. 3, so that transistors in the circuit are turned on/off. As a result, a potential difference between a third node and a second node does not depend on the threshold voltage of a fourth transistor and is determined only by a potential of a data line and a potential of a second wiring. Therefore, an intended current can flow in a display element.
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