| 摘要 |
<P>PROBLEM TO BE SOLVED: To eliminate latch timing difference by on/off of a gear down mode. <P>SOLUTION: A semiconductor device includes a frequency dividing circuit 2 for generating a clock signal CLK2 by performing frequency division of a clock signal CLK1, a logic circuit 4 for generating a chip selection signal CS2 by logically synthesizing a chip selection signal CS1 and the clock signal CLK2, and a command generation circuit 6 for generating a command signal CMD2 on the basis of a command signal CMD1 activated on the basis of the chip selection signal CS2. According to the invention, a command signal can be subjected to a latch operation in synchronization with a clock signal not subjected to frequency division not because a command signal is latched in synchronization with a clock signal subjected to frequency division but because the command generation circuit is activated in synchronization with the clock signal subjected to frequency division. This eliminates difference in latch timing by on/off of the gear down mode. <P>COPYRIGHT: (C)2013,JPO&INPIT |
