发明名称 TEST DEVICE, VERIFICATION MODEL DEVELOPMENT METHOD, AND PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To easily construct a verification environment corresponding to each of various interfaces in a short period. <P>SOLUTION: A test device includes a signal input/output control part 131 for inputting/outputting a signal between the test device and a test object model 11, a storage part 132 for storing a program P which specifies a function of an interface to be executed by the signal input/output control part 131 and a pseudo processor 133 for setting the signal input/output control part 131 according to the program P. A pseudo model 13 which simulates an operation of a device accessed by the test object model 11 is provided. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012226658(A) 申请公布日期 2012.11.15
申请号 JP20110095153 申请日期 2011.04.21
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 FUKUHARA TAKESHI
分类号 G06F17/50;G06F11/22 主分类号 G06F17/50
代理机构 代理人
主权项
地址