发明名称 REPEATER AND CHIP CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To achieve power-saving transmission even when traffics of various delay requests are present in network-on-chip (NoC) mode. <P>SOLUTION: A data transmission system includes a first node which transmits data, a plurality of second nodes which can receive the data transmitted from the first node, and a plurality of repeaters which repeat the data transmitted between the first node and second nodes. A repeater includes a load value processing part which acquires information on a load value associated with at least one of delay times and throughputs of other repeaters connected to a communication bus, and an intensive determination part which determines a second node to receive the data out of the plurality of second nodes by using information on the load values obtained from the respective repeaters and information associated with at least one of the number of repeating stages from the first node to the second node and a length of the data to be transmitted, and determined during the design when a plurality of traffics are generated, and determines a transmission route between the determined second node and the first node. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012226776(A) 申请公布日期 2012.11.15
申请号 JP20120175686 申请日期 2012.08.08
申请人 PANASONIC CORP 发明人 YAMAGUCHI TAKAO;YOSHIDA ATSUSHI;ISHII YUKI
分类号 G06F13/36 主分类号 G06F13/36
代理机构 代理人
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