| 摘要 |
A clock generation system for generating first and second clock signals at slightly different clock frequencies comprising a clock signal generator providing the first clock signal, frequency dividers dividing the clock frequencies by integers to produce auxiliary signals, a timer for measuring a first time lag between first signal edges of the auxiliary signals and a second time lag between second signal edges of the auxiliary signals, a comparator device for providing an error signal by comparing the difference between the measured time lags with a predetermined time value, and a voltage-controlled oscillator controlled in dependent on the error signal to generate the second clock signal. |
