发明名称 |
Method for generating layout pattern of semiconductor device and layout pattern generating apparatus |
摘要 |
In a layout pattern generating method, a specific rework cell used for edition is specified among rework cells and fill cells which are arranged in a semiconductor chip area and a specific pattern of a predetermined shape is generated in a wiring layer for the specific rework cell. A dummy wiring pattern is arranged in at least a part of the wiring layer of and the fill cell and un-specific rework cells among the rework cell other than the specific rework cell. The specific pattern is deleted from the wiring layer for the specifying rework cell. A wiring pattern is arranged in the wiring layer for the specific rework cell by wiring the specific rework cell as a logic cell. |
申请公布号 |
US8312397(B2) |
申请公布日期 |
2012.11.13 |
申请号 |
US20090585085 |
申请日期 |
2009.09.02 |
申请人 |
INOUE TOMOYUKI;RENESAS ELECTRONICS CORPORATION |
发明人 |
INOUE TOMOYUKI |
分类号 |
G06F17/50;H01L23/48;H01L27/18 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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