| 发明名称 |
Selectively reducing the number of cell evaluations in a hardware simulation |
| 摘要 |
An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time. |
| 申请公布号 |
US8311781(B2) |
申请公布日期 |
2012.11.13 |
| 申请号 |
US20090480497 |
申请日期 |
2009.06.08 |
| 申请人 |
GREENBERG STEVEN S.;NGUYEN DU V.;RODRIGUEZ JOSEPH;MENTOR GRAPHICS CORPORATION |
发明人 |
GREENBERG STEVEN S.;NGUYEN DU V.;RODRIGUEZ JOSEPH |
| 分类号 |
G06F17/50;G06F13/00 |
主分类号 |
G06F17/50 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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