| 摘要 |
While a phase of an output clock signal is varied, an input frame pulse is latched based on the output clock signal. Then, by using an output frame pulse, which is a result of the latching, generation of a racing state, which is caused by the phase relation between the output clock signal and the output frame pulse, is detected. Next, a phase adjustment amount is determined so that the phase of the output clock signal of the moment when the racing state is generated is shifted by a period corresponding to half a cycle of the output clock signal. |
