Delay locked loop using hybrid FIR filtering technique and semiconductor memory device having the same

摘要

Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (&Sgr;&Dgr;) modulator to operate at a low frequency without generating false lock and glitch noise.